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ir3521 page 1 v3.03 data sheet xphase3 tm amd svid control ic description the ir3521 control ic combined with an xphase3 tm phase ic provides a full featured and flexible way to implement a complete amd svid power solution. it provides outputs for both the vdd core and vddnb auxiliary planes required by the cpu. the ir3521 provides overall system control and interfaces with any number of phase ics each driving and monitoring a single phase. the xphase3 tm architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. features ? 2 converter outputs for the amd processor vdd core and vddnb auxiliary planes ? supports high speed (hs) i 2 c serial communications ? psi_l serial commands are communicated to a programmable number of phase ics ? 0.5% overall system set point accuracy ? high speed error amplifiers with wide bandwidth of 20mhz and fast slew rate of 10v/us ? remote sense amplifiers provide differential sensing and require less than 50ua bias current ? programmable dynamic vid slew rates ? programmable vid offset (vdd output only) ? programmable output impedance (vdd output only) ? programmable dynamic oc for idd_spike ? programmable per phase switching frequency of 250khz to 1.5mhz ? hiccup over current protection with delay during normal operation ? central over voltage detection and communicati on to phase ics through iin (ishare) pin ? ovp disabled during dynamic vid down to prevent false triggering ? over voltage signal to system with over vo ltage detection during powerup and normal operation ? detection and protection of open remote sense lines ? gate drive and ic bias linear regulator c ontrol with programmable output voltage and uvlo ? small thermally enhanced 32l mlpq (5mm x 5mm) package ordering information device package order quantity IR3521Mtrpbf 32 lead mlpq (5 x 5 mm body) 3000 per reel IR3521Mpbf (samples only) 32 lead mlpq (5 x 5 mm body) 100 piece strips downloaded from: http:///
ir3521 page 2 v3.03 application circuit power saving indicator to vdd phase ics psi_l css/del1 cvdac1 rvcclfb2 css/del2 rosc rvccldrv rthermistor1 rfb13 phsout 26 pwrok 2 enable 3 svc 32 iin2 4 ocset2 7 vosns1+ 14 vdrp1 22 pgood 31 iin1 21 clkout 25 vcclfb 29 vccl 28 phsin 27 vosns2- 12 eaout1 17 vout1 15 vdac1 19 vdac2 6 fb2 9 rosc 23 psi_l 24 svd 1 fb1 16 vccldrv 30 ss/del1 20 vout2 10 ocset1 18 vonsn1- 13 vosns2+ 11 ss/del2 5 eaout2 8 epad ir3521control ic q3 vddnb sense - vddnb sense + rocset1 rvcclfb1 rvdac1 cvccl9 to vddnb remote sense svc phsin 12v pgood phsout vdd sense - vdd sense + svd rocset2 clkout vdac1 ishare1 eaout1 ccp22 ccp21 rcp2 enable 12v cfb2 rfb21 rfb22 3 wire analog control bus to vddnb phase ics to converters to vdd remote sense 2 wire digital daisy chain bus to vdd & vddnb phase ics to phase ic vccl & gate drive bias vccl phase clock input to last phase ic of vdd pwrok ishare2 rvdac2 cvdac2 vdac2 ccp11 rcp1 cdrp1 rfb11 rdrp1 cfb1 ccp12 rfb12 eaout2 load line ntc thermistor; locate close to vdd power stage 3 wire analog control bus to vdd phase ics figure 1 C ir3521 application circuit downloaded from: http:///
ir3521 page 3 v3.03 pin description pin# pin symbol pin description 1 svd svd (serial vid data) is a bidirectional signal that is an input and open drain output for both master (amd processor) and slave (ir3521), requires an external bias voltage and should not be floated 2 pwrok system wide power good signal and input to the ir3521. when asserted, the ir3521 output voltage is programmed through the svid interface protocol. connecting this pin to vccl enables vfix mode. 3 enable enable input. a logic low applied to this pin puts the ic into fault mode. a logic high on the pin enables the converter and causes the svc and svd input states to be decoded and stored, determining the 2-bit boot vi d. do not float this pin as the logic state will be undefined. 4 iin2 output 2 average current input from the output 2 phase ic(s). this pin is also used to communicate over voltage condition to the output 2 phase ics. 5 ss/del2 programs output 2 startup and over cu rrent protection delay timing. connect an external capacitor to lgnd to program. 6 vdac2 output 2 reference voltage programmed by the svid inputs and error amplifier non- inverting input. connect an external rc network to lgnd to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. 7 ocset2 programs the output 2 constant conv erter output current limit and hiccup over- current threshold through an external resistor tied to vdac2 and an internal current source from this pin. over-current protection can be disabled by connecting a resistor from this pin to vdac2 to program the threshold higher than the possible signal into the iin2 pin from the phase ics but no greater than 5v (do not float this pin as improper operation will occur). 8 eaout2 output of the output 2 error amplifier. 9 fb2 inverting input to the output 2 error amplifier. 10 vout2 output 2 remote sense amplifier output. 11 vosen2+ output 2 remote sense amplifie r input. connect to output at the load. 12 vosen2- output 2 remote sense amplifier input. connect to ground at the load. 13 vosen1- output 1 remote sense amplifier input. connect to ground at the load. 14 vosen1+ output 1 remote sense amplifie r input. connect to output at the load. 15 vout1 output 1 remote sense amplifier output. 16 fb1 inverting input to the output 1 error amplifier. converter output voltage can be increased from the vdac1 voltage with an external resistor connected between vout1 and this pin (there is an inte rnal current sink at this pin). 17 eaout1 output of the output 1 error amplifier. 18 ocset1 programs the output 1 constant conv erter output current limit and hiccup over- current threshold through an external resistor tied to vdac1 and an internal current source from this pin. over-current protection can be disabled by connecting a resistor from this pin to vdac1 to program the threshold higher than the possible signal into the iin1 pin from the phase ics but no greater than 5v (do not float this pin as improper operation will occur). 19 vdac1 output 1 reference voltage programmed by the svid inputs and error amplifier non- inverting input. connect an external rc network to lgnd to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. downloaded from: http:///
ir3521 page 4 v3.03 pin# pin symbol pin description 20 ss/del1 programs output 1 startup and over cu rrent protection delay timing. connect an external capacitor to lgnd to program. 21 iin1 output 1 average current input from the output 1 phase ic(s). this pin is also used to communicate over voltage condition to phase ics. 22 vdrp1 output 1 buffered iin1 signal. connect an external rc network to fb1 to program converter output impedance. 23 rosc/ovp connect a resistor to lgnd to program oscillator frequency and ocset1, ocset2, fb1, fb2, vdac1, and vdac2 bias curre nts. oscillator frequency equals switching frequency per phase. the pin voltage is 0.6v during normal operation and higher than 1.6v if over-voltage condition is detected. 24 psi_l digital output to communicate the sy stems power state to phase ics psi_l pin. 25 clkout clock output at switching frequency multiplied by phase number. connect to clkin pins of phase ics. 26 phsout phase clock output at switching frequen cy per phase. connect to phsin pin of the first phase ic. 27 phsin feedback input of phase clock. connect to phsout pin of the last phase ic. 28 vccl output of the voltage regulator, and powe r input for clock oscillator circuitry. connect a decoupling capacitor to lgnd. no external power rail connection is allowed. 29 vcclfb non-inverting input of the voltage regul ator error amplifier. output voltage of the regulator is programmed by the resistor divider connected to vccl. 30 vccldrv output of the vccl regulator error am plifier to control external transistor. the pin senses 12v power supply through a resistor. 31 pgood open collector output that drives low during startup and under any external fault condition. and it monitors output voltages, if any of the voltage planes fall out of spec, it will drive low. connect external pull-up. ( output voltage out of spec is defined as 350mv to 240mv below vdac voltage ) 32 svc svc (serial vid clock) is an open dr ain output of the processor and input to ir3521, requires an external bias voltage and should not be floated epad lgnd local ground for internal ci rcuitry and ic subs trate connection. downloaded from: http:///
ir3521 page 5 v3.03 absolute maximum ratings stresses beyond those listed below may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificat ions are not implied. all voltages are absolute voltages referenced to the lgnd pin. operating junction temperature..0 to 150 o c storage temperature range.-65 o c to 150 o c esd ratinghbm class 1c jedec standard msl rating2 reflow temperature.260 o c pin # pin name v max v min i source i sink 1 svd 8v -0.3v 1ma 10ma 2 pwrok 8v -0.3v 1ma 1ma 3 enable 3.5v -0.3v 1ma 1ma 4 iin2 8v -0.3v 5ma 1ma 5 ss/del2 8v -0.3v 1ma 1ma 6 vdac2 3.5v -0.3v 1ma 1ma 7 ocset2 8v -0.3v 1ma 1ma 8 eaout2 8v -0.3v 25ma 10ma 9 fb2 8v -0.3v 1ma 1ma 10 vout2 8v -0.3v 5ma 25ma 11 vosen2+ 8v -0.5v 5ma 1ma 12 vosen2- 1.0v -0.5v 5ma 1ma 13 vosen1- 1.0v -0.5v 5ma 1ma 14 vosen1+ 8v -0.5v 5ma 1ma 15 vout1 8v -0.3v 5ma 25ma 16 fb1 8v -0.3v 1ma 1ma 17 eaout1 8v -0.3v 25ma 10ma 18 ocset1 8v -0.3v 1ma 1ma 19 vdac1 3.5v -0.3v 1ma 1ma 20 ss/del1 8v -0.3v 1ma 1ma 21 iin1 8v -0.3v 5ma 1ma 22 vdrp1 8v -0.3v 35ma 1ma 23 rosc/ovp 8v -0.3v 1ma 1ma 24 psi_l vccl+ 0.3v -0.3v 1ma 20ma 25 clkout 8v -0.3v 100ma 100ma 26 phsout 8v -0.3v 10ma 10ma 27 phsin 8v -0.3v 1ma 1ma 28 vccl 8v -0.3v 1ma 20ma 29 vcclfb 3.5v -0.3v 1ma 1ma 30 vccldrv 10v -0.3v 1ma 50ma 31 pgood vccl + 0.3v -0.3v 1ma 20ma 32 svc 8v -0.3v 1ma 1ma epad lgnd n/a n/a 20ma 1ma downloaded from: http:///
ir3521 page 6 v3.03 recommended operating conditions for reliable operation with margin 4.75v vccl 7.5v, -0.3v vosen-x 0.3v, 0 o c t j 100 o c, 7.75 k ? r osc 50 k ? , c ss/delx = 0.1uf electrical characteristics the electrical characteristics table show s the spread of values guaranteed within th e recommended operating conditions (unless otherwise specified). typical values (typ) represen t the median values, which are related to 25c. parameter test condition min typ max unit svid interface threshold increasing 0.8025 0.90 0.9975 v threshold decreasing 570 650 750 mv svc & svd input thresholds threshold hysteresis 150 250 400 mv bias current 0v v(x) 3.5v, svd not asserted -5 0 5 ua svd low voltage i(svd)= 3ma 20 300 mv svd fall time, c svd =400 pf 70-30% vddio, 1.425v vddio 1.9v, 1.7mhz operation, note 1 20 40 160 ns svd fall time, c svd =100 pf 3.4mhz operation 20 80 ns pulse width input filter note 1 10 20 20 <100 ns psi_l output output voltage i(psi_l) = 3ma 150 300 mv pull-up resistance (to vccl) 6 10 20 k ? oscillator phsout frequency -10% see figure 2 +10% khz rosc voltage 0.57 0.600 0.630 v clkout high voltage i(clkout)= -10 ma, measure v(vccl) C v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout high voltage i(phsout)= -1 ma, measure v(vccl) C v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % vdrp1 buffer amplifier input offset voltage v(vdrp1) C v(iin1), 0.5v v(iin) 3.3v -8 0 8 mv source current 0.5v v(iin1) 3.3v 2 30 ma sink current 0.5v v(iin1) 3.3v 0.2 0.4 0.6 ma unity gain bandwidth note 1 8 mhz slew rate note 1 4.7 v/ ? s iin bias current -2 -0.2 1 ? a remote sense differential amplifiers unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 0.5v v(vosenx+) - v(vosenx-) 1.6v, note 2 -3 0 3 mv source current 0.5v v(vosenx+) - v(vosenx-) 1.6v 0.5 1 1.7 ma sink current 0.5v v(vosenx+) - v(vosenx-) 1.6v 2 12 18 ma slew rate 0.5v v(vosenx+) - v(vosenx-) 1.6v 2 4 8 v/us vosen+ bias current tbs v < v(vosenx+) < 1.6v 30 50 ua vosen- bias current -0.3v vosenx- 0.3v, all vid codes 30 50 ua vosen+ input voltage range v(vccl)=7v 5.5 v low voltage v(vccl) =7v 250 mv high voltage v(vccl) C v(voutx) 0.5 1 v downloaded from: http:///
ir3521 page 7 v3.03 parameter test condition min typ max unit soft start and delay start delay measure enable to eaoutx activation 1 2.9 3.5 ms start-up time measure enable activation to pgood 3 8 13 ms oc delay time v(iinx) C v(ocsetx) = 500 mv 85 170 325 us ss/delx to fbx input offset voltage with fbx = 0v, adjust v(ss/delx) until eaoutx drives high 0.7 1.4 1.9 v charge current -30 -50 -70 ? a oc delay/vid off discharge currents note 1 47 ? a fault discharge current 2.5 4.5 6.5 ? a hiccup duty cycle i(fault) / i(charge) 7 10 12 ua/ua charge voltage 3.5 3.9 4.2 v delay comparator threshold relative to charge voltage, ss/delx rising note 1 80 mv delay comparator threshold relative to charge voltage, ss/delx falling note 1 120 mv delay comparator hysteresis note 1 40 mv discharge comp. threshold 150 200 300 mv over-current comparators input offset voltage 1v v(ocsetx) 3.3v -35 0 35 mv ocset bias current -5% vrosc(v)*100 0/rosc(k ? ) +5% ? a 2048-4096 count threshold adjust rosc value to find threshold 16 k ? 1024-2048 count threshold adjust rosc value to find threshold 20 k ? error amplifiers vid 1v -0.5 0.5 % 0.8v vid < 1v -5 +5 mv system set-point accuracy (deviation from table 1, 2, and 3 per test circuit in figures 2a & 2b) 0.5v vid < 0.8v -8 +8 mv input offset voltage measure v(fbx) C v(vdacx)). note 2 -1 0 1 mv fb1 bias current -5% vrosc(v)*1000 /rosc(k ? ) +5% ? a fb2 bias current -1 0 1 ? a dc gain note 1 100 110 135 db bandwidth note 1 20 30 40 mhz slew rate note 1 5.5 12 20 v/ ? s sink current 0.4 0.85 1 ma source current 5.0 8.5 12.0 ma maximum voltage measure v(vccl) C v(eaoutx) 500 780 950 mv minimum voltage 120 250 mv open voltage loop detection threshold measure v(vccl) - v(eaout), relative to error amplifier maximum voltage. 125 300 600 mv open voltage loop detection delay measure phsout pulse numbers from v(eaoutx) = v(vccl) to pgood = low. 8 pulses enable input blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns vdac references source currents includes i(ocsetx) -8% 3050*vrosc(v) / rosc(k ? ) +8% ? a sink currents includes i(ocsetx) -8% 2650*vrosc(v) / rosc(k ? ) +8% ? a pgood output under voltage threshold - voutx decreasing reference to vdacx -365 -315 -265 mv downloaded from: http:///
ir3521 page 8 v3.03 note 1: guaranteed by design, but not tested in production note 2: vdacx outputs are trimmed to compensate for error & amp remote sense amp input offset. parameter test condition min typ max unit under voltage threshold - voutx increasing reference to vdacx -325 -275 -225 mv under voltage threshold hysteresis 5 53 110 mv output voltage i(pgood) = 4ma 150 300 mv leakage current v(pgood) = 5.5v 0 10 ? a vccl activation threshold i(pgood) = 4ma, v(pgood) = 300mv 1.73 3.5 v over voltage protection (ovp) comparators threshold at power-up 1.60 1.73 1.83 v voutx threshold voltage compare to v(vdacx) 220 260 285 mv ovp release voltage during normal operation compare to v(vdacx) -20 3 25 mv threshold during dynamic vid down 1.8 1.85 1.9 v dynamic vid detect comparator threshold note 1 25 50 75 mv propagation delay to iin measure time from v(voutx) > v(vdacx) (250mv overdrive) to v(iinx) transition to > 0.9 * v(vccl). 90 180 ns ovp high voltage measure v(vccl)-v(rosc/ovp) 0 1.2 v ovp power-up high voltage v( vccldrv)=1.8v. measure v(vccl)-v(rosc/ovp) 0 0.2 v propagation delay to ovp measure time from v(voutx) > v(vdacx) (250mv overdrive) to v(rosc/ovp) transition to >1v. 150 300 ns iin pull-up resistance 5 15 ? open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(voutx) < [v(vosenx+) C v(lgnd)] / 2 29 62.5 90 mv vosen+ open sense line comparator threshold compare to v(vccl) 86.5 89.0 91.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense line detection source curr ents v(voutx) = 100mv 200 500 700 ua vccl regulator amplifier reference feedback voltage 1.15 1.2 1.25 v vcclfb bias current -1 0 1 ua vccldrv sink current 10 40 ma uvlo start threshold compar e to v(vccl) 89.0 93.5 97.0 % uvlo stop threshold compare to v(vccl) 81.0 85.0 89.0 % hysteresis compare to v(vccl) 7.0 8.25 9.5 % enable, pwrok inputs threshold increasing 1.3 1.65 1.9 v threshold decreasing 0.8 0.99 1.2 v threshold hysteresis 470 620 770 mv bias current 0v v(x) 3.5v, svc not asserted -5 0 5 ua pwrok vfix mode threshold 3.3 v (vccl +3.3)(v) / 2 vc cl v general vccl supply current 3.5 10 15 ma downloaded from: http:///
ir3521 page 9 v3.03 phsout frequency vs rrosc chart phsout frequency vs. rrosc 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 5 1 01 52 02 53 03 54 04 55 05 5 rrosc (kohm) frequency (khz) figure 2 - phout frequency vs. rrosc chart system fault table response open daisy open sense open voltage uvlo (vccl) over voltage disable vid_off svid oc before oc after uvlo (vout) latch uv & en latch en fault latch ss latch no reset recycle vccl then enable recycle enable ss discharge below 0.2v no outputs affected both single both both both single single single disables ea yes no ss/delx discharge yes no flags pgood yes delays 32 clock pulses no 8 phsout pulses no no 250ns blanking time no phsout pulses* ss/delx discharge threshold no additional flagged response no yes, iinx and rosc pins pulled-up to vccl no * pulse number range depends on rosc va lue selected (see specifications table) downloaded from: http:///
ir3521 page 10 v3.03 system set point test the converter output voltage is determi ned by the system set point voltage wh ich is the voltage that appears at the fbx pins when the converter is in regulation. the set point voltage includes error terms for the vdac digital- to-analog converters, error amp input offsets, and remote sense input offsets. the voltage appearing at the vdacx pins is not the system set point voltage. system set point voltage test circuits for outputs 1 and 2 are shown in figures 3a and 3b. cvdac1 + - + - rrosc + - rvdac1 rocset1 + - eaout1 fb1 ocset1 vdac1 vosen1- vosen1+ vout1 lgnd rosc irosc irosc eaout vosns- vdac1 buffer amplifier ifb1 rosc buffer amplifier 1.2v "fast" vdac isink isource ir3521 system set point voltage iocset1 current source generator remote sense amplifier error amplifier irosc figure 3a - output 1 system set point test circuit cvdac2 + - + - rrosc + - rvdac2 rocset2 + - vdac2 ocset2 fb2 eaout2 lgnd vout2 vosen2+ vosen2- irosc rosc vosns- eaout vdac2 buffer amplifier "fast" vdac 1.2v rosc buffer amplifier system set point voltage ir3521 isource isink irosc error amplifier remote sense amplifier current source generator iocset2 figure 3b - output 2 system set point test circuit downloaded from: http:///
ir3521 page 11 v3.03 system theory of operation pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 4. feed-forward voltage mode control with trailing edge modulation is used to provide system control. a voltage type error amplifier with high-gain and wide-bandwidth, located in the control ic, is used fo r the voltage control loop. the feed-forward control is performed by the phase ics as a result of sensing the i nput voltage (fets drain voltage). the pwm ramp slope will change with the input voltage and automatically compensa te for changes in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. clock generator pwm latch current sense amplifier r s share adjust error amplifier reset dominant error amplifier cout ir35121control ic ir3505 phase ic output 1 only pwm comparator pwm comparator - + + + ramp discharge clamp enable bodybraking comparator share adjust error amplifier reset dominant pwm latch current sense amplifier r s ir3505 phase ic ccs remote sense amplifier rcs +- cfb2 cbst + - rcs ccs + - + - cbst + - + - ccp13 rdrp1 rfb12 rfb11 cdrp2 3k clk d q + - + - + - + - + - 3k rcp1 + - + - ccp14 clk d q + - gnd vout1 vdac1 vout1 ishare phsin vosns1- vosns1+ dacin vcc eain gateh iin1 vdrp1 lgnd eaout1 clkout csin- csin+ gatel vccl vcch sw vin fb1 clkin phsout clkin phsout pgnd eain gateh ishare phsin dacin vcc vccl vcch csin- csin+ gatel phsin phsout sw pgnd vid6 irosc vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 gate drive voltage - + + + enable ramp discharge clamp bodybraking comparator ifb1 vdrp1 amp vdac figure 4 - pwm block diagram frequency and phase timing control the oscillator (system clock) is loca ted in the control ic and is progra mmable from 250 khz to 9 mhz by an external resistor. the control ic clock signal (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop. the control ic phase clock output (phsout) is connected to the phase clock input (phsin) of the first pha se ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. the last phase ic (phs out) is connected back to phsin of the control ic to complete the loop. during power up, the control ic sends out clock signal s from both clkout and phsout pins and detects the feedback at phsin pin to determine the phase number and monitor any fault in the daisy chain loop. figure 5 shows the phase timi ng for a four phase converter. downloaded from: http:///
ir3521 page 12 v3.03 phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 5 four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon rece iving the falling edge of a clock, the pwm latch is set and the pwm ramp amplitude begins to increase prompting the low side driver is turned off. after the non-overlap time (gatel < 1.0v), the high side driver is turned on . when the pwm ramp voltage exceeds the error amplifiers output voltage, the pwm latch is reset. this also turns off the high side driver, turns on the low side driver after the non-overlap time and the pwm ramp discharged current is clamped which quickly discharg es the internal capacitor to the output voltage of share adjust amplifie r, in phase ic, until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the common mode input range of the pwm comparator results in 100% duty cycle regardless of the voltage of the pwm ramp. this arrangement guarantees the error amplifie r is always in control and can deman d 0 to 100% duty cycle as required. it also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. the inductor current will increase much more rapidly than decrease in response to load transients. this control method is designed to provide single cycle transient response where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of the archit ecture is that differences in ground or input voltage at the phases have no effect on operation since the pwm ramps are referenced to vdac. figure 6 depicts pwm operating waveforms under various conditions. downloaded from: http:///
ir3521 page 13 v3.03 phase ic clock pulse vdac eain pwmrmp gatel gateh duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid fault) figure 6 pwm operating waveforms body braking tm in a conventional synchronous buck conver ter, the minimum time required to redu ce the current in the inductor in response to a load step decrease is; o min max slew v i i l t ) (* ? ? the slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. the switch node voltage is then forced to decr ease until conduction of the synchronous rectifiers body diode occu rs. this increases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t ? ? ? ) (* since the voltage drop in the body diode is often higher th an output voltage, the inductor current slew rate can be increased by 2x or more. this patent pending technique is referred to as body braking and is accomplished through the body braking comparator located in the phase ic. if the error amplifiers output voltage drops below the vdac voltage or a programmable voltage, this comparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a series resist or and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in figure 7. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r si c sr s v s v ? ? ? ? ? 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chosen so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current through l, and the sense circuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. downloaded from: http:///
ir3521 page 14 v3.03 figure 7 inductor current sensing and current sense amplifier the advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. the output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in series with the inductor, this is the only sense method that can support a single cy cle transient response. other methods provide no information during eit her load increase (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all additional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier is located in the phase ic, as shown in figure 7. its gain is nominally 34 at 25oc, and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltage loop feedback path. the current sense amplifier can accept positive diffe rential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is su mmed with the dac voltage and sent to the control ic and other phases through an on-chip 3k ? resistor connected to the ishare pin. the ishare pi ns of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control ic for voltage positio ning and current limit protection. average current share loop current sharing between phases of the converter is achiev ed by the average current share loop in each phase ic. the output of the current sense amplifier is compared with average current at the share bus. if current in a phase is smaller than the average current, the share adjust amplif ier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output current; if current in a phas e is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the pwm ramp thereby decreasing its duty cycle and output current. the current share amplifier is inte rnally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c o l r l r cs c cs v o current sense amp csout i l v l v cs c downloaded from: http:///
ir3521 page 15 v3.03 ir3521 theory of operation block diagram the block diagram of the ir3521 is shown in figure 8. the following discussions are applicable to either output plane unless otherwise specified. serial vid control the two serial vid interface (svid) pins svc and svd ar e used to program the boot vid voltage upon assertion of enable while pwrok is de-asserted. see table 1 for the 2-bit boot vid codes. both vdac1 and vdac2 voltages will be programmed to the boot vid code until pwro k is asserted. the boot vid code is stored by the ir3521 to be utilized again if pwrok is de-asserted. serial vid communication from the processor is enabled after the pwrok is asserted. addresses and data are serially transmitted in 8-bit words. the ir3521 has three fixed addresses to control vdac1, vdac2, or both vdac1 and vdac2 (see table 6 for addresses). the first data bit of the svid data wo rd represents the psi_l bit and if pulled low will force all phase ics, connected to t he psi_l pin, in to a power-saving mode. the remaining data bits svid[6:0] select the desired vdacx regulation voltage as defined in table 3. svid[6:0] are the inputs to the digital-to-analog converter (dac) which then provides an analog reference voltage to the transconductance type buffer amplifier. this vdacx buffe r provides a system reference on the vdacx pin. the vdacx voltage along with error amplifier and remote sense differential amp lifier input offsets are post-package trimmed to provide a 0.5% system set-point accuracy, as measured in figures 3a and 3b. vdacx slew rates are programmable by properly selecting external series rc compensation networks located between the vdacx and the lgnd pins. the vdacx source and sink currents are derived off t he external oscillator frequency setting resistor, r rosc . the programmable slew rate enables the ir3521 to smoothly transition the regulated output voltage throughout vid transitions. this results in power supply input and output capacitor inrush curr ents along with output voltage overshoot to be well controlled. the two serial vid interface (svid) pins svc and svd can also program the vfix vid voltage upon assertion of enable while pwrok is equal to vccl. see table 2 fo r the 2-bit vfix vid codes. both vdac1 and vdac2 voltages will be programmed to the vfix code. the svc and svd pins require external pull-up biasing and should not be floated. output 1 (vdd) adaptive voltage positioning the ir3521 provides adaptive voltage positioning (avp) on the output1 plane only. avp helps reduces the peak to peak output voltage excursions during load transients an d reduces load power dissipation at heavy load. the circuitry related to the voltage positioni ng is shown in figure 9. resistor r fb1 is connected between the error amplifiers inverting input pin fb1 and the remote sense diffe rential amplifier output, vout1. an internal current sink on the fb1 pin along with r fb1 provides programmability of a fixed offset voltage abov e the vdac1 voltage. the offset voltage generated across r fb1 forces the converters output voltage higher to maintain a balance at the error amplifiers inputs. the fb1 sink current is derived by the external resistor r rosc that programs the oscillator frequency. the vdrp1 pin voltage is a buffered reproduction of t he iin1 pin which is connected to the current share bus ishare. the voltage on ishare represen ts the system average inductor curr ent information. at each phase ic, an rc network across the inductor prov ides current information which is gained up 32.5x and then added to the vdac x voltage. this phase current information is provided on t he ishare bus via a 3k resistor in the phase ics. downloaded from: http:///
ir3521 page 16 v3.03 svd vccl- 1.2v vccldrv vout1 vid off 400k set dominant uv cleared fault latch1 vid3 + - 25k + - s r q dis open daisy idchg 4.5ua vosen2- vosen2+ + - fb2 eaout2 vdac2 ov1 ocset2 ss/del1 iin2 47ua vccl vccl idchg1 vid7 + - 3.9v ss/del cleared fault latch1 reset dominant power-up ok latch delay comparator set dominant vidsel discharge comparator 80mv 120mv ivosen- 0.2v disable2 oc1 after vrrdy ov1 fault latch irosc open sense1 ichg 50ua metal to svid over voltage comparator vdac buffer amplifier error amplifier flt1 svid to svid svid to metal low to high vid3 high to low dly out1 vout1 vid on-the-fly high to low vdac2 vout2 vid off dly out2 uv2 svid enabled dvid2 vid3 vid3 connection to vccl vout1 uv comparator uv2 275mv 315mv vout2 uv comparator + - uv1 sscl fs2 vdac1 + - svid to svid remote sense amplifier dly out1 1.6v 50mv isink isource ivosen2- ivosen2+ 200mv 0.4v dynamic vid2 down detect comparator vccl*0.9 1.4v soft start clamp 260mv oc limit comparator sscl fs1 flt2 vccl reset open sense line2 4 open sense line detect comparators 60mv 1.08v iocset vdac1 vid3 + - irosc ov1_2 + - s r q 47ua idchg2 sscl fs1 + - open control2 s r q q + - u? and2 25k dis vccl + - + - dis 275mv 315mv + - svid to metal + - + + - + - vid3 25k uv cleared fault latch2 set dominant + - + - vccl + - 25k s r q + - s r q read & store pre-pwrok 2 bit vid sscl fs2 dis phsout flt1 dynamic vid1 down detect comparator 8 pulse delay vid3 flt2 irosc open daisy open control loop comparator phsout dly out1 ovlatch 4.5ua dis idchg vfix mode oc2 bf vrrdy disable vrrdy ovlatch vccl uvlo phsout clkout + - epad rosc phsin fault phsin irosc phsout clkout vid0 rosc buffer amplifier current source generator oc1 bf vrrdy open daisy chain 0.6v en en detection pulse2 dis oc delay couter irosc ov2 ov1 reset reset dis dis phsout irosc dis dis oc delay couter dis phsout ov2 vccl dly out2 vrrdy ovlatch 10k psi_l dchg2 dly out2 s r q q svi (seriel vid interface) 0.86 svc vout1 vid off dchg1 flt1 dchg1 svd vccl dis vout2 disable vccl uvlo vccl uvlo detection pulse1 ov1-2 ov1 metal to svid ov2 + - 25k + - ss/del2 back to pre-pwrok 2 bit vid + - pgood + - vccldrv vcclfb vccl enable vosen1- vosen1+ vout1 vdrp1 iin1 ocset1 fb1 eaout1 vdac1 vid3 vccl vccl flt2 vid3 vid7 ivosen- vidsel uv1 irosc disable1 pwrok irosc vout2 vid off delay comparator set dominant 3.9v ss/del cleared fault latch2 vdd error amplifier 1.65v 1v enable comparator vdac buffer amplifier d/a converter over voltage comparator 250ns blanking vout2 vid on-the-fly high to low vccl regulator amplifier vdrp amplifier 0.94 1.2v vccl uvl comparator isink isource remote sense amplifier dis discharge comparator 80mv 120mv reset dominant power-up ok latch ivosen1+ 200mv 1.6v 50mv 0.2v 0.4v vccl*0.9 ivosen1- soft start clamp ifb set dominant oc limit comparator 1.4v flt2 4 open sense line detect comparators 60mv 260mv ov fault latch dis 50ua open sense line1 oc2 after vrrdy iocset ichg vdac2 en 1.08v vccl reset 8 pulse delay detection pulse1 en internal circuit bias + - + - u? and2 25k dchg2 + - open sense2 + - + - vccl uvlo + - 25k flt1 + - + - 25k open control loop comparator vccl vid3 + - + s r q + - open control1 detection pulse2 svc select mode clock memory select mode disable r d . q q s disable por select mode vdd vccl-uvlo figure 8 block diagram downloaded from: http:///
ir3521 page 17 v3.03 vosen1- csin- csin+ iin1 csin- ea out1 isha re vdrp1 phase ic phase ic isha re vout1 + - rfb1 current sense amplifier + - 3k 3k rdrp1 + - ... ... + - vdac vdac remote sense amplifier vdac1 vdac1 fb1 ifb current sense amplifier error amplifier vdrp amplifier control ic vosen1+ csin+ + - figure 9 adaptive voltage positioning + - ea out1 + - iin1 vdac1 ifb vdac1 control ic er r o r amplifier rdrp1 v drp amplifier v drp1 rt rfb12 rfb11 fb1 vosen1+ vout1 vosen1- + - remote sense amplifier figure 10 temperature compensation of output1 inductor dcr downloaded from: http:///
ir3521 page 18 v3.03 output 1 (vdd) adaptive voltage positioning (continued) the voltage difference between vdrp1 and fb1 represents t he gained up average current information. placing a resistor r drp1 between vdrp1 and fb1 converts the gained up current information (in the form of a voltage) into a current forced onto the fb1 pin. this current, which can be calculated using (vdrp1-vdac1) / r drp1 , will vary the offset voltage produced across r fb1 . since the error amplifier will force the loop to maintain fb1 to equal the vdac1 reference voltage, the output regulation voltage w ill be varied. when the load current increases, the adaptive positioning voltage v(vdrp1) incr eases accordingly. (vdrp1-vdac1) / r drp1 increases the voltage drop across the feedback resistor r fb1 , and makes the output voltage lower proportional to the load current. the positioning voltage can be programmed by the resistor r drp1 so that the droop impedance produces the desired converter output impedance. the offset and slope of t he converter output impedance are referenced to vdac1 and are not affected by changes in the vdac1 voltage. output1 inductor dcr temperature compensation a negative temperature coefficient (n tc) thermistor can be used for output1 inductor dcr temperature compensation. the thermistor should be placed close to the output1 inductors and connected in parallel with the feedback resistor, as shown in figure 10. the resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. remote voltage sensing vosen x + and vosen x - are used for remote sensing and connected directly to the load. the remote sense differential amplifiers are high speed, have low input offs et and low input bias currents to ensure accurate voltage sensing and fast transient response. start-up sequence the ir3521 has a programmable soft-start function to lim it the surge current during the converter start-up. a capacitor connected between the ss/del x and lgnd pins controls soft start timing, over-current protection delay and hiccup mode timing. constant current sources and sinks control the charge and discharge rates of the ss/del x . figure 11 depicts the svid start-up sequence. if the enable input is asserted and there are no faults, the ss/del x pin will begin charging, the pre-pwrok 2 bit boot vid c odes are read and stored, and both vdac pins transition to the pre-pwrok boot vid code. the error amplifier output eaout x is clamped low until ss/del x reaches 1.4v. the error amplifier will then regulate the conv erters output voltage to match the v(ss/del x )-1.4v offset until the converter output reaches the 2-bit boot vid code. the ss/del x voltage continues to increase until it rises above the threshold of delay comparator wh ere the pgood output is allowed to go high. the svid interface is activated upon pwrok assertion and the vdac x along with the converter output voltage will change in response to any svid commands. vccl under voltage, over current, or a low signal on t he enable input immediately sets the fault latch, which causes the eaout pin to drive low, thereby turning off t he phase ic drivers. the pgood pin also drives low and ss/del x discharges to 0.2v. if the fault has cleared, the fault latch will be reset by the ss/del x discharge comparator allowing another soft start charge cycle to occur. other fault conditions, such as output over voltage, open vosns sense lines, or an open phase timing daisy chain set a different group of fault latches that can only be reset by cycling vccl powe r. these faults discharge ss/del x , pull down eaout x and drive pgood low. svid off codes turn off the converter by discharging ss/del x and pulling down eaoutx but do not drive pgood low. upon receipt of a non-off svid code the converter w ill re-soft start and transition to the voltage represented by the svid code as shown in figure 11. the converter can be di sabled by pulling the ss/delx pins below 0.6v. downloaded from: http:///
ir3521 page 19 v3.03 svid off transistion svid programmed voltage svid transition startuptime (12v) startdelay vcc enable 1.4v vout pgood 3.92v ss/del 4.0v normaloperation vdacx svid set voltage 2-bit boot vid voltage eaout svid off command svid off command pwrok 2-bit boot vid on-hold 2-bit boot vid on-hold 0.5v svid on transistion svid on command svid on command 1.4v vid on the fly procession 0.8v svcsvd 2-bit boot vid read & store 2-bit boot vid read & store svid transition figure 11 svid start-up sequence transitions downloaded from: http:///
ir3521 page 20 v3.03 serial vid interface protocol and vid-on-the-fly transition the ir3521 supports the amd svi bus protocol and the amd server and desktop svi wire protocol which are based on high-speed i 2 c. svid commands from an amd processo r are communicated through svid bus pins svc and svd. the svc pin of the ir3521 does not have an open drain output since amd svid protocol does not support slave clock stretching. the ir3521 transitions from a 2-bit boot vid mode to svi mode upon assertion of pwrok. the smbus send byte protocol is used by the ir3521 vid-on-the-fly transactions. the ir3521 will wait until it detects a start bit which is defined as an svd falling edge while svc is high. a 7bit address code plus one write bit (low) should then follow the start bit. this address code will be compared against an internal address table and the ir3521 will reply with an acknowledge ack bit if the address is one of the three stored addresses otherwise the ack bit will not be sent out. the svd pin is pulled low by the ir3521 to generate the ack bit. table 4 has the list of addresses recognized by the ir3521. the processor should then transmit the 8-bit data word immedi ately following the ack bit. the first data bit (bit 7), of the svid data word, represents the power state indicator (psi) bit which is passed on to the phase ics via the ir3521 psi_l pin. psi_l is pulled high by an internal 10k resistor to vccl when data bit 7 of an svid command is high. a low, on this bit (bit 7), will pull the psl_pin low and trigger all connected, predetermine, phase ics to turn off. if transitioning from one phase to multiple phases, the last phase ic, or re turning phase ic, should be left on to ensure the fastest possible clock frequency calibration. a sh orter calibration time will help minimize droop at the vdd output when leaving psi_l mode. the remaining data bits svid[6:0] select t he desired vdacx regulation voltage as defined in table 3. the ir3521 replies again with an ack bit once the data is received. if the received data is not a vid-off command, the ir3521 immediately changes the dac analog outputs to the new target. vdac1 and vdac2 then slew to the new vid volt ages. see figure 12 for a send byte example. table 1 C 2-bit boot vid codes table 2 C vfix mode 2 bit vid codes svc svd output voltage(v) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 figure 12 send byte example svc svd output voltage(v) 0 0 1.4 0 1 1.2 1 0 1.0 1 1 0.8 downloaded from: http:///
ir3521 page 21 v3.03 table 3 - amd 7 bit svid codes svid [6:0] voltage (v) svid [6:0] voltage (v) svid [6:0] voltage (v) svid [6:0] voltage (v) 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.5000 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.5000 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.5000 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.5000 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.5000 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.5000 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.5000 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0110 0.5000 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.5000 000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.5000 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.5000 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.5000 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.5000 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.5000 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.5000 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.5000 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.5000 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.5000 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.5000 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.5000 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.5000 001_0101 1.2875 011_0101 0.8875 101_0101 0.5000 111_0101 0.5000 001_0110 1.2750 011_0110 0.8750 101_0110 0.5000 111_0110 0.5000 001_0111 1.2625 011_0111 0.8625 101_0111 0.5000 111_0111 0.5000 001_1000 1.2500 011_1000 0.8500 101_1000 0.5000 111_1000 0.5000 001_1001 1.2375 011_1001 0.8375 101_1001 0.5000 111_1001 0.5000 001_1010 1.2250 011_1010 0.8250 101_1010 0.5000 111_1010 0.5000 001_1011 1.2125 011_1011 0.8125 101_1011 0.5000 111_1011 0.5000 001_1100 1.2000 011_1100 0.8000 101_1100 0.5000 111_1100 off 001_1101 1.1875 011_1101 0.7875 101_1101 0.5000 111_1101 off 001_1110 1.1750 011_1110 0.7750 101_1110 0.5000 111_1110 off 001_1111 1.1625 011_1111 0.7625 101_1111 0.5000 111_1111 off table 4 - svi send byte address table svi address [6:0] + wr description 110xx100b set vid only on output 1 110xx010b set vid only on output 2 110xx110b set vid on both output 1 and output 2 note: x in the above table 4 means the bit could be either 1 or 0. downloaded from: http:///
ir3521 page 22 v3.03 over-current hiccup protection after soft start the over current limit threshold is set by a resistor connected between ocset x and vdac x pins. figure 13 shows the hiccup over-current protection with delay after pgoo d is asserted. the delay is required since over-current conditions can occur as part of normal operatio n due to load transients or vid transitions. if the iin x pin voltage, which is proportional to the average current plus vdac x voltage, exceeds the ocsetx voltage after pgood is asserted, it will initia te the discharge of the capacitor at ss/del x through the discharge current 47ua. if the over-current condi tion persists long enough for the ss/del x capacitor to discharge below the 120mv offset of the delay comparator, t he fault latch will be set which will then pull the error amplifiers output low to stop phase ic switching and will also de-asserting the pgood signal. the ss/del capacitor will then continue to be discharged by a 4.5 ua cu rrent until it reaches 200 mv where the fault latch will rese t to allow another soft start cycle to occur. the output current is not controlled dur ing the delay time. if an over -current condition is again encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. over-current protection (output shorted) 3.87v normal operation ea ocpdelay power-down hiccup over-current protection (output shorted) pgood 3.92v ss/del normal operation start-up with output shorted ocp threshold enable 1.4v iout vout normal start-up 4.0v (output shorted) normal start-up internal oc delay figure 13 hiccup over-current waveforms linear regulator output (vccl) the ir3521 has a built-in linear regulator controller, and only an external npn transistor is needed to create a linear regulator. the output voltage of the linear regulator can be programmed between 4. 75v and 7.5v [?] by the resistor divider at vcclfb pin. the regulator output powers the gate drivers and other circuits of the phase ics along with circuits in the control ic, and the voltage is usually programmed to optimize the converter efficiency. the linear regulator can be compensated by a 4.7uf capacitor at the vccl pin. as with any linear regulator, due to stability reasons, there is an upper limit to the maximum val ue of capacitor that can be used at this pin and its a function of the number of phases used in the multiphase architecture and their switching frequency. figure 14 shows the stability plots for the linear regulator with 5 phases switching at 750 khz. for powering the ir3521 and up to two phase ics an npn tr ansistor in a sot-23 package could be used. for a larger number of phase ics an npn transistor in dpak package is recommended. . vccl voltage must be regulated by a cl osed control loop based on the ir3521s vccl regulator controller in order to keep both vccldrv and vcclfb voltages in the operati ng points that would support correct uvlo operation. no external power rail can be connected to vccl pin. downloaded from: http:///
ir3521 page 23 v3.03 figure 14 vccl regulator stability with 5 phases and phsout equals 750 khz vccl under voltage lockout (uvlo) the ir3521 does not directly monitor v cc for under voltage lockout but instead monitors the system vccl supply voltage since this voltage is used for the gate drive. as vcc begins to rise during power up, the vccldrv pin will be high impedance therefore allowing vccl to roughly follow vcc-npn vbe until vccl is above 94% of the voltage set by resistor divider at vcclfb pin. at this point, the ov x and uv cleared fault latches will be released. if vccl voltage drops below 86% of the set value, the ss/del clear ed fault latch will be set. vid off codes svid off codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down eaout x voltage and discharging ss/del x through the 50ua discharge current, but do not drive pgood low. upon receipt of a non-off svid code the converter will turn on and trans ition to the voltage represented by the svid as shown in figure 10. power good (pgood) the pgood pin is an open-collector output and should hav e an external pull-up resistor. during soft start, pgood remains low until the output voltage is in regulation and ss/del x is above 3.9v. the pgood pin becomes low if enable is low, vccl is below 86% of target, an over current condition occurs for at least 1024 phsout clocks prior to pgood, an over current condition occurs after pgood and ss/del x discharges to the delay threshold, an open phase timing daisy chain condition occu rs, vosns lines are detected open, vout x is 315mv below vdac x , or if the error amp is sensed as operating open loop for 8 phsout cycles. a high level at the pgood pin indicates that the converter is in operation with no fault and ensures the output voltage is within the regulation. pgood monitors the output voltage. if any of the voltage pl anes fall out of regulation, pgood will become low, but the vr continues to regulate its output voltages. the pwrok input may or may not de-assert prior to the voltage planes falling out of specification. ou tput voltage out of spec is defined as 315mv to 275mv below nominal voltage. vid on-the-fly transition which is a voltage plane tran sitioning between one voltage associated with one vid code and a voltage associated with another vid code is not considered to be out of specification. a pwrok de-assert while enable is high results in all planes regulating to the previously stored 2-bit boot vid. if the 2-bit boot vid is higher than the vid prior to pwrok de-assertion, this transition will not be treated as vid on- the-fly and if either of the two outputs is out of spec high, pgood will be pulled down. downloaded from: http:///
ir3521 page 24 v3.03 open voltage loop detection the output voltage range of error amplifie r is continuously monitored to ensure the voltage loop is in regulation. if any fault condition forces the error amplifier output abov e vccl-1.08v for 8 phsout switching cycles, the fault latch is set. the fault latch can only be cleared by cycling the power to vccl. load current indicator output the vdrp pin voltage represents the av erage current of the converter plus the dac voltage. the load current information can be retrieved by using a differential amplifier to subtract vdac1 voltage from the vdrp1 voltage. enable input pulling the enable pin below 0.8v sets the fault latch. forcing enable to a voltage above 1.94v results in the pre-pwrok 2 bit vid codes off the svd and svc pins to be read and stored. ss/del x pins are also allowed to begin their power-up cycles. over voltage protection (ovp) output over-voltage might occur due to a high side mo sfet short or if the output voltage sense path is compromised. if the over-voltage protection comparators sense that either vout x pin voltage exceeds vdac x by 260mv, the over voltage fault latch is set which pulls the er ror amplifier output low to turn off the converter power stage. the ir3521 communicates an ovp condition to the system by raising the rosc/ovp pin voltage to within v(vccl) C 1.2 v. an ovp condition is also communicated to the phase ics by forcing the iin pin (which is tied to the ishare bus and ishare pins of the phase ics) to vc cl as shown in figure 15. in each phase ic, the ovp circuit overrides the normal pwm operation to ensure t he low side mosfet turn-on within approximately 150ns. the low side mosfet will remain on until the ishare pins fall below v(vccl) - 800mv. an over voltage fault condition is latched in the ir3521 and can only be cleared by cycling the power to vccl. during dynamic vid down at light to no load, false ovp tri ggering is prevented by increasing the ovp threshold to a fixed 1.85v whenever a dynamic vid is detected and the difference between output voltage and the fast internal vdac is more than 50mv, as shown in figure 16. the ov er-voltage threshold is changed back to vdac+125mv if the difference between output voltage and the fast internal vdac is less than 50mv. the overall system must be considered when designing for o vp. in many cases the over-current protection of the ac-dc or dc-dc converter supplying the multiphase converte r will be triggered thus prov iding effective protection without damage as long as all pcb traces and components ar e sized to handle the worst-case maximum current. if this is not possible, a fuse can be added in t he input supply to the multiphase converter. downloaded from: http:///
ir3521 page 25 v3.03 after ovp fault latch output voltage (vout) ovp threshold iin (phase ic ishare) vccl-800 mv ovp condition normal operation gateh (phase ic) gatel (phase ic) error amplifier output (eaout) vdac figure 15 - over-voltage protection during normal operation output voltage (vo) vid down normal operation vdac vid ov threshold vdac + 260mv 1.85v normal operation vid up low vid vdac 50mv 50mv figure 16 over-voltage protection during dynamic vid downloaded from: http:///
ir3521 page 26 v3.03 open remote sense line protection if either remote sense line vosen x + or vosen x - is open, the output of remo te sense amplifier (vout x ) drops. the ir3521 continuously monitors the vout x pin and if vout x is lower than 200 mv, two separate pulse currents are applied to the vosen x + and vosen x - pins to check if the sense lines are open. if vosen x + is open, a voltage higher than 90% of v(vccl) will be present at vosen x + pin and the output of open line detect comparator will be high. if vosen x - is open, a voltage higher than 400mv will be present at vosen x - pin and the open line detect comparator output will be high. with either sense line open , the open sense line fault latch will be set to force the error amplifier output low and imm ediately shut down the converter. ss/del x will be discharged and the open sense fault latch can only be reset by cycling the power to vccl. open daisy chain protection the ir3521 checks the daisy chain every time it powers up. it starts a daisy chain pulse on the phsout pin and detects the feedback at phsin pin. if no pulse comes back a fter 32 clkout pulses, the pulse is restarted again. if the pulse fails to come back the second time, t he open daisy chain fault is registered, and ss/del x is not allowed to charge. the fault latch can only be re set by cycling the power to vccl. after powering up, the ir3521 monitors phsin pin for a ph ase input pulse equal or less than the number of phases detected. if phsin pulse does not return within the number of phases in the converter, another pulse is started on phsout pin. if the second started phsout pulse does not return on phsin, an open daisy chain fault is registered. phase number determination after a daisy chain pulse is started, the ir3521 checks the timing of the input pulse at phsin pin to determine the phase number. downloaded from: http:///
ir3521 page 27 v3.03 applications information vdac css/del2 cvdac2 ishare2 rvdac2 vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u105 ir3507 vddnbsen- ccp22 ccp21 rcp2 vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u311 ir3507 vdd 5-phase converter vddnb converter cin5 l7 rdrp11 cvcc7 q15 u318 q23 ccs7 u341 cin4 css/del1 rfb13 ccs8 cvccl10 phsout rcs5 l8 cvccl11 cfb1 cvccl12 l9 rdrp12 rcs4 cbst2 cvcc8 q63 rcs1 q43 cvccl13 cvcc9 u342 rfb12 rcp1 cbst62 q44 ccp12 ccs9 vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u343 ir3507 rocset1 q24 cbst6 ccs10 cvccl14 cin6 rvccldrv v2ea cvccl15 cvcc10 cin1 q16 cin3 u344 cin2 cbst7 rcs6 rvcclfb2 ccs11 q64 l11 l10 ccs12 cvcc12 rosc cvcc11 cvccl16 rvcclfb1 cdrp1 rvdac1 cvdac1 q4 cbst8 ccp11 rfb11 l12 rtherm1 cbst9 rcs3 rcs2 12v vddpwrgd pwrok svc svd cfb2 rfb21 rfb22 enable vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u345 ir3507 vdd sense- vdd sense+ vdd+ vdd- vddsen- vddsen+ cout vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u346 ir3507 vddnb+ vddnb sense- vddnb sense+ vddnb- vddnbsen- vddnbsen+ coutnb phsin vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u347 ir3507 vddsen- vddsen+ v2ea vdac2 rocset2 clkout vddea vgate vddnbsen+ close to power stage phsout 26 pwrok 2 enable 3 svc 32 iin2 4 ocset2 7 vosns1+ 14 vdrp1 22 vrrdy 31 iin1 21 clkout 25 vcclfb 29 vccl 28 phsin 27 vosns2- 12 eaout1 17 vout1 15 vdac1 19 vdac2 6 fb2 9 rosc 23 psi_l 24 svd 1 fb1 16 vccldrv 30 ss/del1 20 vout2 10 ocset1 18 vonsn1- 13 vosns2+ 11 ss/del2 5 eaout2 8 epad ir3521 control ic figure 17 ir3521 \ ir3507 five phases C one phase dual outputs amd svid converter downloaded from: http:///
ir3521 page 28 v3.03 design procedures - ir3521 and ir3508 chipset ir3521 external components all the output components are selected using one output but suitable for both unles s otherwise specified. oscillator resistor r r osc the ir3521 generates square wave pulses to synchronize the phase ics. the switching frequency of the each phase converter equals the phsout frequency, which is set by the external resistor r rosc (use figure 2 to determine the r rosc value). the clkout frequency equals the switching frequency multiplied by the phase number. soft start capacitor c ss/del the soft start capacitor c ss/del programs four different time parameters : soft start delay time, soft start time, pgood delay time and over-current fault latch delay time after pgood. ss/del pin voltage controls the slew rate of the converte r output voltage, as shown in figure 11. once the enable pin rises above 1.65v, there is a soft-start delay time td1 during which ss/del pin is charged from zero to 1.4v. once ss/del reaches 1.4v the error amplifier output is re leased to allow the soft star t. the soft start time, td2, represents the time during which converter voltage rises from zero to pre-pwrok vid voltage and the ss/del pin voltage rises from 1.4v to pre-pwrok vid voltage plus 1. 4v. pgood delay time td3 is the time period from vr reaching the pre-pwrok vid voltage to the pgood signal assertion. calculate c ss/del based on the required soft start time td2. pwrok pre pwrok pre chg del ss v td v i td c ? ? ? ? ? 6 / 10 * 50 *2 *2 (1) the soft start delay time td1 and pgood delay time td 3 are determined by equation (2) and (3) respectively. 6 / / 10 * 50 4.1* 4.1* 1 ? ? ? del ss chg del ss c i c td (2) 6 / / 10 * 50 )4.1 92.3(* )4.1 92.3(* 3 ? ? ? ? ? ? ? ? ? pwrok pre del ss chg pwrok pre del ss v c i v c td (3) once c ss/del is chosen, use equation (4) to calculate the maximum over-current fault latch delay time t ocdel. 6 / / 10 * 47 12.0* 12.0* ? ? ? del ss dischg del ss ocdel c i c t (4) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac down-slope sr down can be programmed by the external capacitor c vdac as defined in (5), where i sink is the vdac buffer sink current. the resistor r vdac is used to compensate vdac circuit and is determined by (6). the up and down slow are equal due to symmetrical sink and source capabilities of the vdac buffer. downloaded from: http:///
ir3521 page 29 v3.03 down sink vdac sr i c ? (5) 2 15 10 2.3 5.0 vdac vdac c r ? ? ? ? (6) over current setting resistor r ocset the inductor dc resistance is utilized to sense the induct or current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c, and therefore the maximum inductor dcr can be calculated from (7), where r l_max and r l_room are the inductor dcr at maximum temperature, t l_max, and room temperature, t l _ room, respectively. )] ( 10* 3850 1[ _ _ 6 _ _ room l max l room l max l t t r r ? ? ? ? ? ? (7) the total input offset voltage (v cs_tofst ), of the phase ics current sense am plifier, is the sum of input offset (v cs_ofst) of the amplifier itself and that cr eated by the amplifier input bias curre nt flowing through the current sense resistor r cs . cs csin ofst cs tofst cs r i v v ? ? ? ? _ _ (8) the over-current limit is set by the external resistor r ocset as defined in (9). i limit is the required over-current limit. i ocset is the bias current of ocset pin and can be calc ulated with the equation located in the electrical characteristics table. g cs is the gain of the curr ent sense amplifier. k p is the ratio of inductor peak current over the average current in each phase and can be calculated using equation (10). ocset cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1( [ _ _ ? ? ? ? ? ? (9) n i f v l v v v k o sw i o o i p / )2 /( ) ( ? ? ? ? ? ? (10) vccl programming resistor r vcclfb1 and r vcclfb2 since vccl voltage is proportional to the mosfet gate driver loss and inversely proportional to the mosfet conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. vccl linear regulator consists of an external npn transistor, a ce ramic capacitor and a programmable resistor divider. pre- select r vcclfb1 , and calculate r vcclfb2 from (11). 23.1 23.1* 1 2 ? ? vccl r r vcclfb vcclfb (11) no load offset setting resistor rfb11, rfb13, rtherm1 and adaptive voltage positioning resistor rdrp11 for output1 define r fb_r as the effective offset resistor at room temperature equals to r fb11 //(r fb13 +r therm1 ). given the offset voltage v o_nlofst (offset above the dac voltage) and calculat ing the sink current from the fb1 pin i fb1, using the equation in the electrical characteristics t able, the effective offset resistor value, r fb1, can be determined from equation (12). downloaded from: http:///
ir3521 page 30 v3.03 1 _ _ fb nlofst o r fb i v r ? (12) adaptive voltage positioning lowers the converter voltage by r o *i o, where r o is the required output impedance of the converter. pre-select feedback resistor r fb, and calculate the droop resistor rdrp, o cs room l r fb drp r n g r r r ? ? ? * _ _ 11 (13) calculate the desired effective feedback re sistor at the maximum temperature r fb_m using (14) max l cs o drp m fb r g n r r r _ 11 _ * ? ? ? (14) a negative temperature const ant (ntc) thermistor r therm1 is required to sense the temperature of the power stage for the inductor dcr thermal compen sation. pre-select the value of r therm. r therm must be bigger than r fb_r at room temperature but also bigger than r fb_m at the maximum allowed temperature. r tmax1 is defined as the ntc thermistor resistance at maximum allowed temperature, t max. r tmax1 is calculated from (15). )] 1 1 (* [ * _ _ 1 1 1 room max l therm therm tmax t t b exp r r ? ? (15) select the series resistor r fb13 by using equation (16). r fb13 is incorporated to linearize the ntc thermistor which has non-linear characteristics in t he operational temperature range. 2 ) ( )) /( * *) ( * (*4 ) ( 1 1 _ _ _ _ 1 1 1 1 2 1 1 13 tmax therm mfb rfb mfb rfb tmax therm tmax therm tmax therm fb r r r r r r r r r r r r r ? ? ? ? ? ? ? ? (16) use equation (17) to determine rfb11. 1 13 _ 11 1 1 1 therm fb r fb fb r r r r ? ? ? (17) downloaded from: http:///
ir3521 page 31 v3.03 idd dynamic oc limit capacitor the latest amd processors require two over current limits: one for normal ther mal design current (tdc) operation and the other for system idd_spike. tdc ov er-current is set by following instructi ons outlined in the over current setting resistor rocset section. idd_spike occur when the load cu rrent exceeds the tdc for a very short duration (10 ms). figure 18 shows the boundaries of an event. the current over a moving average of 10 ms does not exceed the tdc limit. higher idd-spike will last for a shorter duration. figure 18 showing idd_spike boundaries the idd_spike over current threshold can be implement ed by incorporation a properly sized capacitor between the ocset (18) and the in1 (21) pins (see figure 19). figure 19 c iddspike and r ocset form a high pass filter 1234567891 0 time (ms) current (a) iddspike tdc ocp-tdc ocp-iddspike phase ic 1 phase ic 2 phase ic 3 phase ic 4 iout iout iout iout iin vdac ocset1 r vdac c vdac control ic ocset comparator r ocset c iddspike high-pass filter downloaded from: http:///
ir3521 page 32 v3.03 when a step load is applied, the capacitor acts as a shor t-circuit, at that instant, and pushes the ocset signal up by ? v (i.e. change in iin) instantaneously. after an increase in its level, the ocp signal starts decaying exponentially towards its original value. the rate of decay is determ ined by the rc time constant. the vr will enter hiccup mode when the ocset signal falls below the iin value. the followi ng equation (18) is use to calculate the ideal capacitor value: , _ _ tdc spike oc spike oc oc spike spike idd i i i i in r t c ? ? ? ? ? (18) where, t spike_oc = idd_spike oc time (choose >1.5ms), r oc = oc resistor (tdc), i spike = idd_spike max, i oc = tdc oc threshold, i tdc = thermal design current. the following graph shows a dynamic oc response with t spike set for 1.5ms. figure x: figure 20 showing dynamic oc response tdc oc threshold idd_spike boundary idd_spike oc threshold tspike_oc tdc oc threshold idd_spike boundary idd_spike oc threshold tspike_oc downloaded from: http:///
ir3521 page 33 v3.03 ir3508 external components inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to sense the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor c cs represents the inductor current. if the two time constants are not the same, the ac component of the capacitor voltage is different from that of the real inductor current. the time constant mismatch does not affect the average current shar ing among the multiple phases, but affe ct the current signal ishare as well as the output voltage during the load current tran sient if adaptive voltage positioning is adopted. measure the inductance l and t he inductor dc resistance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c rl r ? (19) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf-1uf decoupling capacitors are require d at vcc and vccl pins of phase ics. downloaded from: http:///
ir3521 page 34 v3.03 voltage loop compensation the adaptive voltage positioning (avp) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. li ke current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and split s the double poles of the power stage, which make the voltage loop compensation much easier. adaptive voltage positioning lowers the converter voltage by r o *i o, where r o is the required output impedance of the converter. the selection of compensation types depends on the output capacitors used in the converter. for the applications using electrolytic, polymer or al-polymer capacitors and running at lower frequency, type ii compensation shown in figure 21(a) is usually enough. while for the applications using only ceramic capacitors and running at higher frequency, type iii compensation shown in figure 21(b) is preferred. for applications where avp is not requi red, the compensation is the same as for the regular voltage mode control. for converter using polymer, al-polymer, and ceramic capacitors, which have much higher esr zero frequency, type iii compensation is requir ed as shown in figure 18(b) with r drp and c drp removed. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 21 voltage loop compensation network type ii compensation for avp applications determine the compensation at no load, the worst case condition. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, and determine r cp and c cp from (20) and (21), where l e and c e are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. 2 2 ) * * * 2( 1 * 5 ) 2( c c i fb e e c cp r c f v r c l f r ? ? ? ? ? ? ? ? ? (20) cp e e cp r c l c ? ? ? 10 (21) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. downloaded from: http:///
ir3521 page 35 v3.03 type iii compensation for avp applications determine the compensation at no load, the worst case condition. assume the rc, resistor and capacitor across the output inductors, and l/dcr time constant matches, the crossover frequency and phase margin of the voltage loop can be estimated by (22) and (23), where r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f ? ? ? * * 2 1 ? (22) ? ? 180 )5.0 tan( 90 1 ? ? ? a c (23) choose the desired crossover frequency fc around fc1, es timated by (22), or choose fc between 1/10 and 1/5 of the switching frequency per phase. the components should be selected to ensure the close loop gain slope is -20db /dec around the crossover frequency. choose resistor r fb1 according to (24), and determine c fb and c drp from (25) and (26). fb fb r r 2 1 1 ? to fb fb r r 3 2 1 ? (24) 1 4 1 fb c fb r f c ? ? ? ? (25) drp fb fb fb drp r c r r c ? ? ? ) ( 1 (26) r cp and c cp have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. determine r cp and c cp from (27) and (28). i fb e e c cp v r c l f r 5 ) 2( 2 ? ? ? ? ? ? ? (27) cp e e cp r c l c ? ? ? 10 (28) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation for non-avp applications resistor r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase margin c. calculate k factor from (29), and determine the component values based on (30) to (34), )]5.1 180 ( 4 tan[ ? ? ? c k ? ? (29) k v f c l r r i c e e fb cp ? ? ? ? ? ? ? 5 ) 2( 2 ? (30) cp c cp r f k c ? ? ? ? 2 (31) cp c cp r k f c ? ? ? ? ? 2 1 1 (32) downloaded from: http:///
ir3521 page 36 v3.03 fb c fb r f k c ? ? ? ? 2 (33) fb c fb c k f r ? ? ? ? ? 2 1 1 (34) current share loop compensation the internal compensation of current share loop ensures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. downloaded from: http:///
ir3521 page 37 v3.03 design example C amd five + one phase dual output converter (figure 17) specifications input voltage: v i =12 v dac voltage: v dac =1.2 v no load output voltage offset for output1: v o_nlofst =15 mv output1 current: i o1 =95 adc output2 current: i o1 =20 adc output1 over current limit: i limit1 =115 adc output2 over current limit: i limit2 = 25 adc output impedance: r o1 =0.3 m ? dynamic vid slew rate: sr=3.25mv/us over temperature threshold: t max =110 oc power stage phase number: n1=5, n2=1 switching frequency: f sw =520 khz output inductors: l1=120 nh, l2=220 nh, r l1 = 0.52m ? , r l2 = 0.47m ? output capacitors: poscaps, c=470uf, r c = 8m ? , number cn1=9, cn2=5 ir3500 external components oscillator resistor r rosc once the switching frequency is chosen, r rosc can be determined from figure 2. for switching frequency of 520khz per phase, choose r osc =23.2k ? . soft start capacitor c ss/del determine the soft start capacitor fr om the required soft start time. uf vboot i td c chg del ss 1.0 0.1 10 * 50 * 10 *2 *2 6 3 / ? ? ? ? ? the soft start delay time is ms i c td chg del ss 2.2 10 * 50 1.1* 10 *1.0 1.1* 1 6 6 / ? ? ? ? ? the pgood delay time is ms i v c td chg boot del ss 6.3 10 * 50 )1.1 1 92.3(* 10 *1.0 )1.1 92.3(* 3 6 6 / ? ? ? ? ? ? ? ? ? the maximum over current fault latch delay time is ms i c t dischg del ss ocdel 638 .0 10 * 47 12.0* 10 *1.0 12.0* 6 6 / ? ? ? ? ? downloaded from: http:///
ir3521 page 38 v3.03 vdac slew rate programming capacitor c vdac and resistor r vdac nf sr i c down sink vdac 1.14 10*2.3 10 2.45 3 6 ? ? ? ? ? , choose c vdac =22nf ohm c r vdac vdac 1.7 10 2.3 5.0 2 15 ? ? ? ? ? over current setting resistor r ocset the output1 over current limit is 115a and the output2 over current limit is 25a . from the electrical characteristics table can get the bias current of ocset pin (i ocset ) is 26ua with r osc =23.2 k ? . the total current sense amplifier input offset voltage is around 0mv, calculate constant k p, the ratio of inductor peak current over average current in each phase, 38.0 5/ 115 )2 10* 520 12 10* 120 /(2.1)2.1 12( / )2 /( ) ( 1 3 9 ? ? ? ? ? ? ? ? ? ? ? ? ? ? n i f v l v v v k limit sw i o o i p 19.0 25 )2 10* 520 12 10* 220 /(2.1)2.1 12( 2 3 9 ? ? ? ? ? ? ? ? p k ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 1 _ ? ? ? ? ? ? ? ? ? ? ? ? ? k 6.21 ) 10*26 /( 34*)38.1 10*52.0 5 115 ( 6 3 ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 2 _ ? ? ? ? ? ? ? ? ? ? ? ? ? k 4.18 ) 10*26 /( 34*)19.1 10* 47.0 1 25 ( 6 3 vccl programming resistor r vcclfb1 and r vcclfb2 choose vccl=7v to maximize the co nverter efficiency. pre-select r vcclfb1 =20k ? , and calculate r vcclfb2. ? ? ? ? ? ? k vccl r r vcclfb vcclfb 26.4 23.1 7 23.1* 10*20 23.1 23.1* 3 1 2 no load offset setting resistor rfb11, rfb13, rtherm1 and adaptive voltage positioning resistor rdrp11 for output1 define r fb_r is the effective offset resistor at room temperature equals to r fb11 //(r fb13 +r therm1 ). given the offset voltage v o_nlofst above the dac voltage, calculate the sink current from the fb1 pin i fb1 = 26ua using the equation in the electrical characteristics tabl e, then the effective offset resistor value r fb_r 1 can be determined by: ohm i v r fb nlofst o r fb 577 10*26 10*15 1 6 3 1 _ _ ? ? ? ? ? adaptive voltage positioning lowers the converter voltage by r o *i o, where r o is the required output impedance of the converter. pre-select feedback resistor r fb, and calculate the droop resistor rdrp, downloaded from: http:///
ir3521 page 39 v3.03 kohm r n g r r r o cs room l r fb drp 7.6 10*3.0*5 34* 10*52.0* 577 * 1 3 3 _ _ ? ? ? ? ? ? ? in the case of thermal compensation is requir ed, use equation (14) to (17) to select the r fb network resistors. ir3508 external components inductor current sensing capacitor c cs and resistor r cs choose c cs 1=c cs 2=0.1uf, and calculate r cs, ? ? ? ? ? ? ? k c rl r cs l cs 3.2 10*1.0 ) 10*52.0/( 10* 120 1 6 3 9 ? ? ? ? ? ? ? k c rl r cs l cs 7.4 10*1.0 ) 10*47.0/( 10* 220 2 6 3 9 downloaded from: http:///
ir3521 page 40 v3.03 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plane lgnd. ? connect the ground tab under the control ic to lgnd plane through a via. ? separate analog bus (eain, dacin and ishare) from digital bus (clk in, phsin, and phsout) to reduce the noise coupling. ? place vccl decoupling capacitor vccl as close as possible to vccl and lgnd pins. ? place the following critical components on the same layer as control ic and position them as close as possible to the respective pins, rosc, rocset, rv dac, cvdac, and css/del. avoid using any via for the connection. ? place the compensation components on the same layer as control ic and position them as close as possible to eaout, fb, vo and vdrp pins. avoid using any via for the connection. ? use kelvin connections for the remote voltage sense signals, vosns+ and vosns-, and avoid crossing over the fast transition nodes, i.e. switching n odes, gate drive signals and bootstrap nodes. ? avoid analog control bus signals, vdac, iin, and especia lly eaout, crossing over the fast transition nodes. ? separate digital bus, clkout, phsout and phsin from the analog control bus and other compensation components. downloaded from: http:///
ir3521 page 41 v3.03 pcb metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to prevent shorting. ? lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensure s a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? four 0.30mm diameter vias shall be placed in t he center of the pad land and connected to ground to minimize the noise effect on the ic. ? no pcb traces should be routed nor vias placed under any of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb resu lting in poor solder joints to the ic leads. downloaded from: http:///
ir3521 page 42 v3.03 solder resist ? the solder resist should be pulled away from the me tal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulli ng the s/r 0.06mm will alwa ys ensure nsmd pads. ? the minimum solder resist width is 0.13mm. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. ? four vias in the land pad should be tented or plugged from bottom boardside with solder resist. downloaded from: http:///
ir3521 page 43 v3.03 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, t he stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease t he incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3521 page 44 v3.03 package information 32l mlpq (5 x 5 mm body) ja =24.4 o c/w, jc =0.86 o c/w downloaded from: http:///
ir3521 page 45 v3.03 data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa te l: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com downloaded from: http:///

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